This paper describes the design and measured performance of 16-40GHz power amplifier MMICs fabricated with an advanced state of the art 0.15um Gallium Nitride (GaN) process technology. The process features a 50um thick Silicon Carbide (SiC) substrate and compact transistor layouts with individual source grounding vias (ISV). The designs utilize a non-uniform distributed power amplifier (NDPA) topology with Ruthroff connected output transformers. The 3-stage single-ended amplifier demonstrates 4.1-8.7 W of output power over a 16-40GHz bandwidth. For the second MMIC two of the single-ended amplifiers are balanced to produce 7.0-16.0 W over the same frequency range.

Fully-integrated highly linear Ka-band differential power amplifiers (PA) are designed in 28-nm CMOS process. A Class-AB topology is used to increase the efficiency and linearity. For proper operation of the class-AB amplifier, harmonic control circuits are introduced to minimize the 2nd harmonics at the drain and source of the transistor. By adopting this structure, the common source / 2-stack PAs achieve PAE of 27% / 25%, and EVM of 5.17% / 4.2% and ACLR_E-UTRA of -33 dBc / -33 dBc, respectively, at an average output power of 9.5 dBm / 14.2 dBm at 28.5 GHz for a 20-MHz bandwidth, 64QAM, and 7.5-dB PAPR LTE signal.

A stacked power amplifier (PA) with a power-added efficiency (PAE) of higher than 40% in U-band is implemented in GlobalFoundries 45 nm CMOS SOI technology. The PA achieves a relatively good power performance from 42 to 54 GHz. At 46 GHz the PA, biased under 6 V, measures a saturated output power (PSAT) of 22.4 dBm, a linear gain of 17.4 dB, a peak PAE of 42%, and a drain efficiency (DE) of 49%. Under a smaller supply voltage of 4.8 V, PSAT is reduced to 20 dBm while DE and peak PAE increase to 53% and 45%, respectively. As experimentally demonstrated, utilizing a triple cascode cell and suppression of parasitic capacitance of transistors through combining transistor layouts contribute to the improved performance of the PA.

A 60-GHz 1.2-V wideband power amplifier (PA) with a compact 8-way radial power combiner implemented in 90-nm CMOS process is presented in this paper. The transformer-based radial power combiner with 1-dB insertion loss at 60 GHz and 0.043-mm2 compact size is designed for high output power combining and wideband load-pull matching. This PA achieves saturated output power (PSAT) of 20.6 dBm, maximum power added efficiency (PAEmax) of 20.3% and 20.1-dB small-signal gain (S21) at 60 GHz. The PA maintains 20-dBm PSAT with the PAEmax better than 17.3% within 50-64 GHz, and it has the 3-dB bandwidth (3-dB B.W) of 24.5 GHz (41.8-66.3 GHz). The chip area without pads is 0.432 mm2. To the author's best knowledge, this PA presents a widest frequency range (50-64 GHz) with the 20-dBm PSAT and above 17% PAEmax in 60-GHz CMOS PA.

This paper presents a wide band 110GHz power amplifier in thin digital 65nm Low Power (LP) CMOS technology. The amplifier consists of 4 stages of single-ended common source (CS) amplifiers with Shielded Microstrip Line (S-MSL) based inter-stage and input-out matching networks. To address the decoupling issue of single-ended stages, a compact decoupling structure based on distributed inter-digitized MOM capacitor is implemented. The full wave electromagnetic simulations of the decoupling structure show an input impedance of 0.47-j0.12 ohm at 110GHz. The measured maximum small signal gain of the power amplifier is 17.8dB at 109GHz with a 3 dB bandwidth of 13 GHz (104-117 GHz). The OP1dB is 8.25dBm, while the saturated output power is 9.6dBm at 112.5 GHz with 10.4% power added efficiency (PAE). The amplifier occupies an area of 340x400um^2 including RF pads.

A broadband S-band high efficiency internally matched 240 W GaN high power amplifier (HPA) has been developed. To obtain wider operating bandwidth and higher efficiency HPA, an output matching network with shunt inductors and 2nd harmonic reflection open-stubs connected by transmission lines is employed. To verify this methodology, we fabricated an S-band HPA and the output power of 240 W and the power added efficiency of 54.4 % over from 2.6 to 3.4 GHz were achieved. To the authors’ knowledge, this is one of the widest bandwidth performances among the ever-reported S-band GaN HPAs over 100 W output power.

An active bi-directional power dividier/combiner circuit based on a distributed topology is proposed. The use of bi-directional amplifiers (BDAs) provides both dividing and combining functions within the same circuit. By utilizing a distributed topology composed of BDAs and artificial transmission lines, a wide operational bandwidth (2-22 GHz) and a large, flat power gain (9 dB) were achieved under DC power consumption of 100 mW. The maximum amplitude and phase imbalances were 0.7 dB and 3˚, respectively.

An output matching network with high-order harmonic matching is proposed for wideband power amplifier (PA) design, which realize wideband fundamental load-pull matching and first two order harmonic matching for efficiency improvement simultaneously. The proposed power amplifier is implemented in 0.18-μm CMOS process. Within the 3dB small signal bandwidth from 2.8 to 6 GHz, it achieves more than 20.8 dBm Psat and 20.3 dBm OP1dB, while peak power added efficiency (PAE) are from 37 to 44%, and PAE at P1dB are from 33 to 38%. The circuit shows the best efficiency performance compared with the published broadband CMOS PAs.

A novel two-way prototype which can suppress the second harmonic is proposed for concurrent dual-band power amplifier (PA). Each way with two filters makes it only operate in a band so that the harmonics can be filtered well and the intermodulation components of the two frequencies will not be generated. A 0.9/1.8 GHz dual-band PA is designed and fabricated. Measurement results show that the ratio of fundamental to second harmonic power are respectively -44.5 dBc and -41.5 dBc, and the intermodulation components are as low as noise. The output power of both bands is 41.0 dBm, and efficiency is 73.0%, while the corresponding gain are respectively 15.5 dB and 17.5 dB, under concurrent mode. The PA is stimulated with a concurrent 20-MHz wide-band signal, the ACPR are -34.5 dBc and -32.0 dBc with average power of 35 dBm, respectively.

In this work we present linearity improvement of a 10 W GaN HEMT PA using dynamic gate biasing technique for flattening the transfer phase of the PA according to the instantaneous input power. Dynamic Vgs calculation was based on one-tone power sweep measurement with static bias. The results are showing 5.6-7.7 dB better ACPR and 4.2-4.9 percentage points better EVM compared to the reference static bias PA with same average Pout. Furthermore, 1.7-2.7 dB higher output power with 1.3-8.5 percentage points higher PAE has been achieved compared to the reference static bias with ACPR better than 40 dBc. Moreover, it has been shown that static measurement of this GaN PA can be used for a good prediction of the PA behavior under dynamic operation.

The generation of high frequency signals into the terahertz range is dominated by photonic-based systems pushing the development of ultra-broadband wireless communication links. Recently, photonic integrated circuits have been proposed to implement different photonic signal generation techniques offering different semiconductor laser structures. Here we present for the first time a dual wavelength source for optical heterodyning based on hybrid integration of complex passive and active InP elements on an optical polymer platform. The chip integrates two external cavity lasers, each with an InP gain chip coupled to a polymer phase and Bragg gratings sections, combined with a Y-junction. Each laser has a wavelength tuning range over 20 nm, enabling the generation of signals from tenths of GHz up to several THz with MHz resolution. We demonstrate the generation of a 330 GHz free-running beatnote has a linewidth of few MHz ( < 3 MHz)

We present a high-performance terahertz radiation source based on a photomixer integrated with a logarithmic spiral antenna that utilizes plasmonic contact electrodes to offer record-high continuous-wave terahertz radiation powers. Use of plasmonic contact electrodes allows increasing terahertz photocurrents fed to the antenna, resulting in significantly higher terahertz radiation power levels compared to conventional photomixers. We experimentally demonstrate continuous-wave terahertz radiation with a radiation frequency tuning range of more than 2 THz and a radiation power of 17 μW at 1 THz, exhibiting a 3-fold higher radiation power level compared to the state-of-the art.

We present a high-power, broadband terahertz emitter that operates at telecommunication optical pump wavelengths at which high-performance and compact fiber lasers are commercially available. The presented terahertz emitter is a novel large area photoconductive emitter that utilizes a two-dimensional array of plasmonic nano-antennas fabricated on an ErAs:InGaAs substrate to offer significantly higher terahertz radiation powers compared to the state-of-the art. We demonstrate record-high terahertz radiation power levels as high as 300 µW over a 0.1 – 5 THz frequency range, exhibiting two orders of magnitude higher efficiencies compared to state-of-the art photoconductive terahertz emitters operating at telecommunication optical pump wavelengths.

A novel heterodyne terahertz detection scheme based on plasmonic photomixing is presented, which is capable of offering high terahertz detection sensitivity levels and detection bandwidths at room temperature. The presented heterodyne detection scheme replaces terahertz mixer and local oscillator of conventional heterodyne receivers with a plasmonic photomixer pumped by an optical local oscillator provided by two wavelength tunable lasers with a terahertz frequency difference. We demonstrate a first proof-of-concept heterodyne receiver prototype designed for operation at 0.1 THz frequency range, which offers 4-orders of magnitude higher detection sensitivities compared to the state-of-the art.

We present a fully-integrated and electronically-controlled millimeter-wave beam-scanning through a vanadium dioxide (VO2) reconfigurable meta-surface. The meta-surface consists of a two-dimensional array of reconfigurable cross-shape meta-surface fabricated on a thin VO2 film. Joule heating electrodes are integrated with the meta-surface structure, which allows controlling the temperature of the VO2 layer. By controlling the applied voltage to the heating electrodes of each row across the meta-surface we tune the dielectric properties of the VO2 layer for each row. Hence, we electronically control the phase shift that is introduced by each row across the structure. As a result by using the phase array concept and by applying proper voltages to the rows across the array, we obtain fully-electronic millimeter-wave beam-scanning. With the presented structure we are able to achieve 40.4º of continuous beam-scanning at f = 95 GHz.

Metamaterials have demonstrated the capability to perform advanced modulation at terahertz (THz) frequencies and may be formed into spatial light modulators (SLMs). The ability to control metamaterials electronically permits advanced modulation states difficult to implement with other SLMs. We implement both quadrature amplitude modulation and frequency diverse modulation and present results of active metamaterial spatial light modulators used for communications and coded aperture imaging at THz frequencies. We overview metamaterial digital spatial light modulators and discuss potential applications within the terahertz regime.

This paper presents a phase noise filter technique enabled by the delay-line and PD/CP based frequency discriminator with fully automatic calibration. It features wide bandwidth and insensitivity to amplitude noise. At low/high gain mode, it achieves 10.6/15 dB phase noise suppression with -116/-114.9 dBc/Hz sensitivity at 1 MHz offset, respectively. The suppression bandwidth is 100 kHz-10 MHz with input operating frequency range of 9.99-10.10 GHz. This proof-of-concept design is fabricated in a 65 nm CMOS process with the chip area of 1.68 mm × 1.5 mm. The circuit consumes 102 mW power.

In this paper, a fully-integrated 4×4 digital-to-impulse radiating array with a programmable delay at each element is reported. Coherent spatial combining from 16 elements is successfully demonstrated. The combined signal from 16 elements achieves a jitter of 230fsec, a pulse-width of 14psec, and an EIRP of 17dBm. Each array element is equipped with an 8-bit digitally-programmable delay that provides a step resolution of 200fsec and a dynamic range of 20psec. The chip is implemented in a 65nm bulk CMOS process.

This paper presents a fractional 88-105 GHz frequency synthesizer module developed to support THz spectrometer instruments for planetary exploration. The presented module features low power operation and a small form factor to be compatible with the demanding payload requirements of NASA planetary missions. The core of the module is a CMOS System-on-Chip (SoC) containing a 50 GHz phase-lock loop and W-band frequency doubler, driven by a direct digital frequency synthesizer (DDFS) and DAC to provide finely tuned reference frequencies allowing fractional operation. The chip contains a wide range of calibration functions for temperature and radiation exposure compensation. The demonstrated module draws a total of 152 mW of power from a USB connection and provides coverage from 88-105 GHz with output powers up to -15 dBm. The offered mid-band phase noise is measured at 89.5 dBc/Hz evaluated at 1 MHz offset from the carrier.

This paper presents a low phase noise and high gain Gm boosted Colpitts Voltage Controlled Oscillator (VCO) that covers a 9.8% continuous tuning range spanning 18.79 to 20.73 GHz. The tank was modified to facilitate the VCO to maintain low phase noise despite having high gain. Designed and implemented in IBM 0.13µm SiGe BiCMOS8hp technology, the measured phase noise at 10 MHz offset ranges between -140 to -132.5 dBc/Hz throughout the entire tuning range with a maximum gain of 2 GHz/Volt. The VCO is optimized for a 76 to 81 GHz FMCW radar when followed with a frequency multiplier by four. The VCO core consumes 29mA from a 2V regulator.

This paper presents a novel gm enhancement method to minimize the oscillation start-up current in a CMOS voltage-controlled oscillator (VCO). A class-B biasing is achieved by extending the capacitive-feedback network, resulting in a larger output amplitude and hence a lower phase-noise. The flicker-noise of the tail current source is further minimized by self–biased switching current-sources. The proposed VCO is demonstrated in a 65 nm CMOS technology. The prototype measurement result shows a tuning range of 16 % with a phase-noise of -119.2dBc/Hz at 1 MHz offset from a 5.7 GHz carrier frequency. The VCO consumes only 3.6 mA from a 1.2 V supply.

This paper presents a 2-stage Class-F-1 power amplifier in 0.13 μm SiGe BiCMOS process, achieving 43% peak PAE and 18 dBm Psat at 40.5 GHz. The PA utilizes simple but effective λ/4-transformer based 2nd harmonic-tuning load and relies on a native low capacitive reactance to short all other higher-order harmonics. This reduces the harmonic load complexity significantly and loss thereof, exceeding PAE over 40% at 39.5-42 GHz. The PA achieves >17 dB small signal gain, >15 dB power gain, and 16 dBm OP-1dB at 39-43 GHz. The Pout for

This paper presents a wide bandwidth fully integrated CMOS power amplifier (PA) suitable for pulse-mode operation. The CMOS PA was implemented in a 90-nm process with core size of 1 mm^2. A pulse-modulated polar transmitter for LTE femtocell applications was constructed with this switching CMOS PA using the aliasing-free digital pulse-width modulation technique. With conventional memoryless digital predistortion, the polar transmitter achieved 23.5% efficiency and 19.5-dBm output power at 2.4 GHz. Moreover, the proposed transmitter can also pass the -45-dBc ACLR requirement over a wide frequency range from the first channel in downlink band-1 to the last channel in downlink band-7 for LTE home femtocell base stations.

This paper presents a new modified envelope delta-sigma (DS) based transmitter architecture with good linearity and efficiency performance without applying any linearization techniques. For the proposed transmitter setup, a pulsed load modulation (PLM) amplifier is implemented and used for its high power efficiency at the back-off power levels. For high efficiency performance of the PA and maintaining the linearity of the system, an envelope DS modulator is utilized to quantized signals prior to the PA. Simulation results also show that higher coding efficiency of the quantized signal is achievable employing the envelope DS modulator instead of its Cartesian counterpart. To validate the proposed technique, a transmitter prototype is implemented and tested with standard signals with various pick-to-average power ratios (PAPRs). The average drain efficiency of about 45% and 44% are achieved for a 3MHz LTE signal with 7dB PAPR and a 1.25MHz WiMAX signal with and 7.9dB PAPR, respectively.

A highly efficient three-level class-G modulated RF power amplifier (PA) is presented. The PA is designed to operate as downlink amplifier in the 1800-1900 MHz LTE-band. At 1.85 GHz the peak output power under continuous wave excitation is 48.2 dBm (66 W). The system achieves an overall efficiency of more than 50% when amplifying a 20 MHz OFDM signal with 9 dB peak-to-average power ratio at 40 dBm (10 W) average output power and over 15 dB gain. In combination with digital predistortion the class-G modulated PA can achieve an ACLR of -36.2 dB and an EVM of 2.1%. The class-G modulation enables excellent efficiency due to absence of a linear amplifier in the modulator stage. The efficiency improvement due to the three-level class-G modulation reaches 18.7 percentage points.

A 3.8-4.8GHz single-chip in-band full-duplex (FD) transceiver with self-interference cancellation (SIC) is reported. The RX has a noise figure (NF) of 3.1dB/6.3dB at 10MHz/50kHz IF with TX and SIC off. The 1/f noise corner is 60kHz, more than 10× lower compared to prior works. Moreover, for the first time, the operation of RX and SIC is demonstrated when a co-integrated TX is working at the same time and generating >20dBm output power. When TX and SIC is on, at -10dBm SI power, the NF is 7.3dB/10.4dB at 10MHz/50kHz IF. This is lower by 5.5dB/9.6dB at 10MHz/50kHz IF compared to the NF with SIC off.

The Super-Lattice Castellated Field Effect Transistor (SLCFET) uses a super-lattice in the channel region to form multiple parallel current paths in conjunction with castellations etched into that super-lattice to provide a sidewall gate structure. The sidewall gate permits the gate applied electric field to penetrate between the parallel 2DEG layers, allowing the carriers to be depleted out prior to avalanche breakdown within the material, as would occur with a conventional gate structure. Using an AlGaN/GaN super-lattice, we report on this method as a way to scale RF switch performance, decreasing ON resistance without significantly increasing OFF capacitance, with a median measured ON resistance of 0.38 Ω-mm and a median measured OFF capacitance of 0.21 pF/mm, leading to an RF switch figure of merit, Fco=2.0 THz. Wideband SPDT RF switch performance over a 0.1-20 GHz bandwidth with |-30| dB of isolation has been achieved.

Novel and realistic application of hot-via interconnects to millimeter-wave active and power MMICs is demonstrated for the first time. Power amplifier MMICs in the 80- and 100-GHz range were successfully designed, assembled, and characterized for wire-bond free chip interconnect technology. With hot-via RF transitions, compact E-band power amplifier MMICs directly soldered onto evaluation boards demonstrate 22-dB gain and over 28 dBm output power in the ETSI band of 81-86 GHz, with little performance degradation compared to reference circuits probed with traditional front-side RF pads. Similarly, a broadband amplifier, when interconnected to its matching PCB, delivers 13-dB of gain in the W-band, and 21-dBm P1dB. To the author’s knowledge, this work represents the highest frequency demonstration of any soldered millimeter-wave hot-via active circuits onto standard PCBs, with remarkable measured power performance, closely equaling that of ideally front-side RF probed MMICs.

Abstract — This paper presents the design of a fully integrated high-efficiency wideband RF power amplifier at 5GHz band for WLAN standard and other wideband applications. Employing a novel on chip wideband matching technique, the PA achieves the maximum drain efficiency better than 60% for more than 1GHz of usable bandwidth from frequency range of 4.8GHz to 5.85GHz at PSAT of 35dBm. For standard modulation, drain efficiency is more than 24% at 23dBm, with 80MHz standard 256QAM WLAN 802.11ac signal, while maintaining the required EVM below -32dB. The proposed fully integrated class E/F PA was fabricated in 0.25um GaN-on-Sic technology and occupies only 2.2mm x 1.1mm.

This paper reports on a very low phase-noise GaN HEMT cavity oscillator at 8.5 GHz based on a reflection amplifier with electronic gain control. The gain control functionality is essential in order to control the open loop gain, which is critical for the phase noise performance. A large loop gain forces the oscillator in deep compression, resulting in increased noise conversion and degraded phase noise. On the other hand, a sufficient gain margin is mandatory to ensure satisfaction of the oscillation condition with margin that covers temperature drift and individual spread. The gain control uses varactors to change the output termination of a reflection amplifier. The loop gain can then be set independently of the bias point of the active device and the position of the metal cavity. Phase noise of -136 dBc/Hz@ 100 kHz off-set is achieved, which is comparable to a mechanically tuned oscillator in the same process.

Distorsion and attenuation occuring during Track and Hold transition is challenging for Track-and-hold amplifier (THA) with bandwidth larger than 10GHz . Moreover, singleended to differential conversion is mainly required for radar applications. A single-ended/differential wideband THA circuit with a specific clock delay line buffer is proposed. The demonstrated technique is robust and results in a low distortion and low attenuation sampling operation for an input power of -5dBm over the entire bandwidth. The validity of the concept has been demonstrated by a circuit realized in 130nm SiGe BiCMOS. Furthermore, the proposed compensated balun allows to achieve a low phase difference and gain variation (0.25dB) in the [1-26]GHz frequency band. An effective bandwidth of 26GHz was measured with a Total-Harmonic-Distorsion (THD) of ?-51dB@10GHz and ?-39dB@20GHz at a sampling rate of 2.5GS/s.

This paper presents a 500-750 GHz waveguide based single-pole single-throw (SPST) switch achieving a 40% bandwidth. The switch is based on a MEMS reconfigurable surface which can block the wave propagation in the waveguide by short-circuiting the electrical field lines of the TE10 mode. The switch is designed for optimized isolation in the blocking state and for optimized insertion loss in the non-blocking state. The measurement results of the first prototypes show better than 15 dB isolation in the blocking state and better than 3 dB insertion loss in the non-blocking state for 500-750 GHz. The higher insertion loss is mainly attributed to the insufficient metal thickness and surface roughness on the waveguide sidewalls. Two switch designs with different number of blocking elements are fabricated and compared. The switch bandwidth is limited by the waveguide only and not by the switch technology.

Heterodyne and direct detection radiometer receivers at 94 GHz have been realized in a 130 nm Si/SiGe BiCMOS process. They have been assembled into fully selfcontained metal housings with a waveguide flange for the antenna connection. The receivers, which employ a SiGe LNA with below 4 dB noise figure, show overall responsivities of 620 µV/K and 380 µV/K respectively.

In this paper we present a synthetic waveguide integrated in a commercial BiCMOS back-end-of-line, employing artificial dielectrics (ADs) to reduce the component size. The AD is realized by employing floating pillars using the various layers available in the technology, thus fulfilling metal density rule and boosting the effective permittivity of the host medium (i.e., SiO2) to 12.5. The impact of the AD translates in a 56% width reduction of the waveguide, for the same cutoff frequency. The structure provides 1.6dB of losses per guide wavelength (g) at 300GHz and more than 30dB suppression below 180GHz, avoiding the need of filters in multiplication stages.

We present a tunable high-Q two pole waveguide bandpass filter at 110GHz. The demonstrated filter has record performing insertion loss (2dB) and tuning range (11GHz) in the W band (75-110GHz). A sub-micron resolution piezo electric stepper motor is used to actuate a thin film which forms the ceiling of the resonant cavities. This sub-micron actuation effectively tunes the center frequency of the filter. This tunable filter has a variety of uses such as a front-end bandpass filter for multi-band communications, as a filter for rejecting intermodulation products on tunable systems or as a channel select filter.

A low-loss and low-cost Silicon Image Guide (SIG) platform for realization of high performance sub millimeter-wave and THz integrated systems is proposed. The implementation of an extremely low-loss bend and 3-dB power divider, as typical examples of high performance passive components realizable by the proposed technology, are presented. The SIG structures are fabricated using the fast and mask-free laser machining technique. The measured average insertion loss of the SIG is remarkably 0.035 dB/mm over the frequency range of 110-170 GHz. A very low-loss bend with a bending loss less than 0.25 dB/90degree at 150 GHz for the curvatures with the radius as small as 2 mm is practically demonstrated

This paper presents a linear Doherty power amplifier (PA) with adaptive bias circuit for average power-tracking (APT) operation. The Doherty PA is linked with a multi-level DC-DC converter for APT in all amplifiers including the carrier-, peaking-, and drive-amplifiers. The Doherty PA delivers high efficiencies at all average output power levels. Also, the high linearity is maintained with various collector biases by the adaptive bias circuits. For demonstration purposes, the PA with adaptive bias circuits is implemented using an InGaP/GaAs HBT and Texas Instruments' LM3290 product is used for the multi-level DC-DC converter. The PA is tested at 1.9 GHz using a fully loaded LTE signal with 16-QAM, 7.5-dB PAPR, and 10-MHz bandwidth. The PA delivers a PAE of 45.7\%, an EVM of 2.65\%, and an ACLR of -35.3 dBc at an average output power of 27.5 dBm, and the efficiency of whole back off regions are significantly improved.

This paper presents a 80W high gain and broadband Doherty power amplifier (DPA) with symmetrical devices. A novel architecture is used to eliminate the interaction of second harmonic impedances caused by load modulation and provide high efficiency at output back-off (OBO) and saturation. Under a 10% duty cycle pulse excitation from 3.35-3.50 GHz, experimental results show the DPA delivers 49.1-49.5 dBm output power with a drain efficiency (DE) of 50.2%-55.1% at 8 dB OBO and achieves a gain of 14.6-14.9 dB at an output power of 41 dBm. When extend the bandwidth to 3.3-3.6 GHz, the DPA can attain a measured DE higher than 40.9% at an OBO of 8 dB with a saturated power of 48.5-49.5 dBm. For a 2-carrier 40-MHz signal with a peak-to-average power ratio (PAPR) of 8 dB, the adjacent channel leakage ratio (ACLR) is -30 dBc at 41 dBm average output power at 3.45 GHz.

In this paper, a novel Doherty power amplifier (PA) design method that enables high efficiency and high linearity simultaneously is developed. The output combiner network parameters are solved to satisfy boundary conditions required for high efficiency, and linear gain and phase responses. The proposed method is experimentally verified by a 2.14 GHz prototype PA, fabricated using two identical 15 W GaN HEMT devices. For a 8.6 dB peak to average power ratio 10 MHz LTE signal, the PA presents an average power added efficiency of 40%, and an adjacent power leakage ratio of –41 dBc without any linearization.

A novel output combining network for concurrent dual-band Doherty power amplifier (DPA) is proposed. The proposed output combiner employs a modified Π-network, which enables the absorption of main and peaking transistors’ output parasitics over an extended frequency range and eliminates the need for offset lines that compromises the achievable bandwidth. In addition to performing the impedance inversion, the proposed combiner incorporates the biasing feeds and presents small low-frequency impedances to both transistors in order to improve the DPA linearizability when driven with concurrent dual-band modulated signals. A 50-W dual-band DPA demonstrator was successfully designed to operate across two bands, 2.05–2.30GHz and 3.2–3.62GHz. It achieved more than 49% and 47% drain efficiency at 6-dB output back-off over the two bands, and was successfully linearized under single and dual-band modulated signal stimuli.

A novel methodology for designing concurrent dual-band Doherty power amplifier (DPA) is presented in this paper. The required impedance conditions of the carrier amplifier to achieve high-efficiency performance at back-off region are discussed from a new perspective. A novel combine network with direct-matching impedance transformer is then presented to support the load modulation conditions for concurrent dual-band operations. A 1.8-2.6 GHz dual-band Doherty amplifier employing commercial GaN devices is then designed and implemented to validate the proposed method. The fabricated power amplifier (PA) achieves 72% and 60% efficiency for saturation operation at 1.8 and 2.6 GHz, respectively. For the 6 dB back-off region, the measured efficiencies are 63% and 51% in the two designed bands.

In this paper, the series of continuous working modes of power amplifier(PA) are introduced into Doherty PAs. The series of continuous modes contain the continuous working modes between Class-B/J and Class-F continuums. By judiciously optimizing the phase of carrier output matching network, the series of continuous working modes can be got by carrier PA at peaking output. A highly efficient broadband Doherty PA based on series of continuous modes is implemented with operation band over 1.65-2.4GHz. At 6dB power back-off and maximum output power, the drain efficiencies of this Doherty PA are 46%-57% and 60.12%-76.24%, respectively. The gain and output power characteristics of the DPA at saturation are 11.5-12.1dB and 43.55-45.1dBm, respectively.

This paper presents a novel dual-input Doherty-Outphasing Power Amplifier (DOPA) architecture that combines the efficiency advantages of Doherty and Outphasing amplifiers in power back-off (PBO). The proposed architecture, utilizes Doherty operation from peak power to -6dB PBO and mixed-mode outphasing from -6 to -14 dB PBO. A 2.14 GHz 112W GaN DOPA has been designed to demonstrate the concept, it provides 66% peak efficiency and more than 50% efficiency over a 12 dB PBO range.

In this paper a cross-polarized multi-channel W-band radar for contactless velocity measurement of turbulent flows in industrial pipes is presented. The system is based on three FMCW radar channels with separate RX/TX, which are fed into wideband orthomode transducers. For maximum SNR each channel has two focused dielectric lens antennas resulting in three narrow beams through the flow. The reflectors are implemented by means of wideband trans-polarizing reflectors, allow high precision cross-polarization (HV,VH) time-of-flight measurements through the pipe with reduced influence of the pipe’s window reflections. The flow velocity is extracted by correlation of the passing times of the flow’s vortexes through the three radar beams. Each radar channel is based on a SiGe MMIC transceiver chip allowing highly linear fractional-N FMCW sweep generation from 68 to 93GHz. In this paper an overview of the main system components is given and first single channel measurement results are presented.

This paper presents a newly invented multi-section auto-focus millimeter wave holography scheme by using a single frequency signal. Both simulation and demonstration results are provided and compared with conventional holography and wideband imaging. This new multi-section auto-focus holography scheme demonstrates much better imaging resolution than conventional holography, has the similar imaging quality as the wideband imaging, but with one order less processing time and much simpler hardware requirement.

This work describes development and implementation of a Schottky varactor diode array for sideband generation at 1.6 THz. The array integrates 100 planar Schottky diodes into an array of bowtie antennas to act as a tunable phase-shifter for reflected submillimeter-wave radiation. Design and fabrication of the array are discussed in detail. Measurements performed to characterize the array indicate that 20° of phase shift is achievable as the diode bias voltage is swept between 0.3 and –4 Volts, yielding an estimated sideband conversion loss of 26 dB.

We report on a characterization method of the emission spectrum of mm-Wave and terahertz sources without the use of additional terahertz instruments. It exploits the reciprocal properties of these radiating sources. This method can be applied to any source equipped with an antenna. It has been used to characterize the spectral response of two distinct sources. The first is a 0.35 THz ring oscillator and the second is a 0.55 THz Colpitts oscillator, both implemented in a 65 nm CMOS technology. The results of the proposed characterization method have been verified with an FTIR spectrometer and a commercial harmonic mixer.

100-mV 44-uW 2.4-GHz LNA is realized by using TSMC 16 nm FinFET Plus technology. The design approach includes: (1) sub-threshold design at the gate terminal (2) near-triode design at the drain terminal and (3) stability design from nconditionally stable to conditionally stable. With a voltage gain of 10.8dB and a NF of 3.0dB, ULV energy harvesting for IoTs can be enabled.

This paper presents a fully integrated 802.11a/n LNA. Unlike published SOI LNAs, Body-Contacted transistor has been chosen for its superior linearity performance. Traditional drawback of Body-Contacted transistor is Gate to Body parasitic capacitances impacting the NF; they have been minimized through careful layout. The paper highlights Body-Contact interest before going through LNA optimization, including transistor sizing, high Q inductors implementation and layout. The LNA is processed in 0.13-µm partially-depleted silicon-on-insulator (PD-SOI) CMOS with 1.2V supply voltage. The LNA provides 12.7dBm IIP3 high linearity, for a 9dB gain, 1.34dB NF for 9.6mW power consumption.

This work proposes an asymmetric SPDT transmit/receive (T/R) switch co-optimized with a low-noise amplifier (LNA) tailored to X-band operation and implemented in an 0.13 μm SiGe BiCMOS technology. The switch achieves high power handling capability in transmit mode, while maintaining low insertion loss, by utilizing asymmetric topology. In receive mode, low noise is obtained by integrating a lumped-element matching network used simultaneously as a noise matching network for the LNA, as well as a lumped λ/4 transformer for the SPDT isolation. In transmit mode, the SPDT-LNA results in 1.1 dB insertion loss, 26 dB isolation, and 26.9 dBm output P1dB at 10 GHz. In receive mode, the measured noise figure is 1.9 dB with 15 dB gain at 10 GHz. To the authors’ best knowledge, these results are the lowest noise figure and highest transmit output P1dB for any Si-based SPDT-LNA reported at X-band.

A 33 to 41-GHz Low Noise Amplifier (LNA) with a 3-dB Noise Figure (NF) using 0.12-um InAlGaN/GaN HEMT was developed. The LNA consists of a two-stage common-gate amplifier with current reuse topology in order to obtain a high gain with low power consumption. The developed LNA achieved 15-dB gain, and an input return loss of less than -10 dB. The measured NF was 3 dB, and the power consumption was 280 mW. The measured OIP3 and OP1dB were 24 dBm and 13 dBm at 38 GHz under a supply voltage of 20 V. The chip size of the LNA is 1×0.7 mm2.

A compact E-band amplifier circuit has been developed for use in ultra-high capacity point-to-point communication links. The millimeter-wave monolithic integrated circuit (MMIC) consists of a two-stage low-noise amplifier (LNA), a 10 dB line coupler, an integrated detector diode and a single-stage variable gain amplifier (VGA). The multifunctional MMIC was realized by using a 50 nm InAlAs/InGaAs based metamorphic high electron mobility transistor (mHEMT) technology in combination with grounded coplanar waveguide topology and cascode transistors, thus leading to a very low noise figure in combination with high gain and large operational bandwidth at millimeter-wave frequencies. The fabricated LNA circuit achieved a maximum gain of 37 dB at 78 GHz and more than 34 dB in the frequency range from 69 to 98 GHz. Furthermore, a room temperature noise figure of 2.3 dB and a detector responsivity of 39.000 V/W have been obtained at the frequency of operation.

A novel mixer topology by using gate and drain pumped with combining drain terminals of nMOS devices is proposed to enhance LO/IF operation bandwidth in 90-nm CMOS. With 0.6 mW of dc power, this mixer achieves peak conversion gains (CGs) -6.2 dB, -6.1 dB, -8.6 dB, and -7.2 dB at LO frequencies of 30, 50, 60, and 90 GHz, respectively. At LO power 2.3 dBm and LO frequency of 30 GHz, IF 3-dB bandwidth is 26 GHz. When LO power is 4.2 dBm at LO frequency of 90 GHz, the mixer has IF 3-dB bandwidth of 16 GHz. The IP1dB is at least 2 dBm from 30 to 90 GHz. The chip occupies 0.389 mm^2. Comparison with other published works, this mixer demonstrates extremely wide bandwidth LO/IF for astronomy application.

Integrated 60-GHz reflection-type phase shifter (RTPS) with near-constant insertion-loss for phased array transceivers is demonstrated in this paper. The RTPS is based on a cascaded couplers structure and implemented in a standard 0.12 µm SiGe BiCMOS process, using CMOS features only. The phase shifter is controlled by a 6-bit DAC and achieves >200° phase variation across the 57-66 GHz band with less than ±0.5 dB insertion loss variation over all phase states. The measured insertion loss at 60 GHz is 7.4±0.25 dB. Measured RMS phase error is less than 2.6° and the RMS gain error is less than 0.3 dB over the 57–66 GHz range. The IC occupies area of 400 x 700 μm2 (0.28 mm2), excluding pads

A 2-to-67 GHz distributed N-type complementary metal oxide semiconductor (NMOS)-heterjunction bipolar transistor (HBT) Darlington mixer using 0.18 μm SiGe BiCMOS process is presented in this paper. A distributed topology is adopted to achieve broad RF bandwidth with good radio frequency (RF) and local oscillation (LO) input return losses. A hybrid NMOS-HBT Darlington cell is utilized in the mixer gain cell design to extend RF bandwidth with low LO driving power as compared to the conventional distributed drain mixer. The proposed mixer exhibits a broad RF factional bandwidth of 188.4%, a maximum conversion gain of 5 dB, a LO power of 0 dBm, and a compact chip size of 0.76 × 0.55 mm2. The total dc power consumption is 17.5 mW.

A 60 GHz passive phase shifter with low phase and amplitude error is presented in this paper. Unlike other passive phase shifter, this phase shifter consists of 2 switch type phase shifter (STPS), vector generator and vector selector to achieve 4 bit (22.5° phase resolution) and full 360° phase synthesizing. From 57-66 GHz, the measured insertion loss is 17 dB. The RMS phase and amplitude error are < 5° and 0.5 dB, respectively, and the gain flatness is ±0.5 dB with 0-mW dc power consumption. The total chip size is 0.168 mm^2. Beside, this phase shifter can operate without extra digital to analog convertor (DAC). To the authors knowledge, this phase shifter demonstrate the lowest RMS gain error and gain flatness among 60 GHz phase shifter.

A double balanced (DBM) CMOS mixer providing high linearity is presented in this paper. A cross-coupled pair used in the IF stage of the mixer to dynamically inject current into the to mixer provide a high linearity. The proposed DBM was fabricated using a standard 130-nm CMOS process and was tested on-wafer. The double balanced mixer delivers 10 dB conversion gain, 9.5 dBm IIP3, and input P 1dB of -2.4 dBm. RF bandwidth of the proposed mixer is 6 GHz, covering 0.5 GHz to 6.5 GHz with IF bandwidth of 300 MHz. RF to IF and LO to IF isolation are also better than 59 dB in the whole frequency band. The circuit uses an area of 0.015 mm 2 excluding bonding pads and draw 4.5mW from a 1.2V supply.

This paper describes a highly-integrated 122-GHz system-on-chip radar sensor in a SiGe BiCMOS technology. The chip includes a radar transceiver and two on-chip antennas utilizing a novel antenna design approach that allows the use of the localized backside etching technique without compromising the mechanical stability of the chip. The implemented double folded-dipole antenna achieves an antenna gain of 6 dBi with a radiation efficiency of 54%. The transceiver is equipped with a 61-GHz VCO that is complemented with a frequency doubler to generate the transmit signal. The receive path includes an LNA, a 90 degree coupler, two passive subharmonic mixers and variable gain amplifiers. Radar measurements with static as well as moving targets were done to show the applicability of the developed system

This paper presents a 90-100 GHz heterodyne radiometer module based on a CMOS receiver system-on-chip (SoC). The SoC contains a frequency synthesizer, downconverter, RF&IF; amplification, as well as a wide range of auto-leveling and calibration, and LO stabilization functions. To provide low-noise operation the CMOS SoC is packaged within a waveguide block and mated with an InP MMIC based LNA pre-amplifier. The complete module delivers noise performance below 400ºK and is capable of less than 0.5ºK NEΔT with an integration time of 50 ms. The entire radiometer instrument consumes 257mW of power and weighs only 334 grams.

This paper presents a low-noise SiGe radiometer at 136 GHz developed in an IBM 90 nm SiGe BiCMOS technology. The radiometer chip consumes 45 mW and results in a minimum NEP of 1.4 fW/Hz1/2 with a peak responsivity of 52 MV/W at 136 GHz and a noise equivalent temperature difference (NETD) of 0.25K (= 3.125 mS). To the best of our knowledge, this is the lowest temperature resolution in silicon technologies at D-band.

In this work, we present a multi-frequency illumination transmitter for microwave imaging radar reflectometry (MIR) diagnostics of thermonuclear fusion plasmas. The transmitter is able to illuminate 8 tones simultaneously. To improve the PA stability, the cross-coupled capacitor based neutralization technique is adopted. Diplexer based power combining is first invented to realize heterogeneous frequency power combining. Each of the 8 frequencies demonstrates more than 0 dBm of saturation power tunable from 62 to 78 GHz. The transmitter features multiple mixers and power amplifiers for power boosting of each frequency. The entire TX occupies 2.14 mm2 chip area and dissipates about 733 mW.

This RF-power module is a building block for a multi-kilowatt high-efficiency power amplifier system. The module employs five GaN-FET class-F RF power amplifiers with a low-loss Gysel splitter and combiner. Envelope Elimination and Restoration is used to maintain efficiency over a wide range of amplitudes. It achieves an efficiency of 79 percent for power outputs from 380 to 650 W, and an efficiency of 70 percent for all outputs above 90 W. The drive power is only 12 W.

A transmission-line loading network for class-E amplifiers is presented. In this work, a GaN FET device with a parasitic drain capacitance of 4-pF is used at 1-GHz design frequency for 20-W output power at 20-V DC supply voltage. A finite inductive reactance DC-feed class-E amplifier output network is designed based upon wire-lines and then modified using transmission-line transforms. The final network topology is managed so that it contains specific transmission-line impedances suitable for breadboarding employing air-suspended brass-bars so that no dielectric is used. The network presents the proper impedance at the device intrinsic drain and at the same time serves as broadband matching to 50-Ohms. The resultant measured performance of 80% efficiency or higher and flat output power over wide bandwidth (760-1060 MHz) is presented.

This paper presents a push-pull Doherty power amplifier (PPDPA) with an octave bandwidth. It includes balanced to unbalanced (balun) transformers which are custom designed to limit the dispersion of the second harmonic terminations seen by the main and auxiliary transistors. When integrated into the broadband impedance inverter, the resulting combiner network allows for maintaining proper load modulation and consequently high efficiency at back-off for more than an octave bandwidth. A mixed-signal PPDPA demonstrator was successfully designed using two packaged 90 Watt GaN transistors. It demonstrated drain efficiencies of 52-64 % and 51-58 % at full and 6 dB back-off powers across a fractional bandwidth of 80 % (0.6 GHz-1.4 GHz). It also maintained an output power of about 51.5 dBm +/- 1.5 dB.

A UHF outphasing transmitter, based on continuous-mode Class E power amplifiers (PAs) and implementing a constant-gain envelope tracking (ET) strategy, is presented in this paper. Drain terminating and biasing networks are designed to provide near optima impedance values at the fundamental and higher order harmonics to the selected GaN HEMT device. A high-efficiency wideband performance, 80% for a 630-890 MHz range, is obtained, besides being amenable for load-modulation through a compact outphasing scheme, incorporating a series Chireix combiner and an impedance transformer. Once characterized in a pure output power phase-coding regime, the observed limitation in dynamic range is overcome by operating the amplifiers in continuous class J mode, while forcing the load impedance to follow a constant-gain trajectory. A 1c-WCDMA signal, with peak-to-average power ratio (PAPR) of 8.4 dB is shown to be reproduced, satisfying the linearity requirements, with an average efficiency of 58%.

This paper presents a 90º hybrid-coupler based passive phase interpolator that is utilized to design a W-band 5-bit phase shifter in 0.13 μm SiGe BiCMOS process. In the proposed phase shifter, amplitude weighting is made first by VGAs. Then, a 90o-hybrid performs I/Q phase splitting and phase interpolation to synthesize all four quadrant phases. In this way, the accuracy of the phase synthesis is less vulnerable to an amplifier loading effect.The phase shifer is optimized for a transmitter application and the measured peak-to-peak gain variation for all 5-bit phase states is 4.8-9.7 dB at 94 GHz. The measured rms gain error is < 1.6 dB over 93-108 GHz. The measured RMS phase error is < 1.5º at 94 GHz. The input and output P-1dB is -13 dBm and -4.7 dBm, respectively, at 94 GHz. The chip consumes 37 mW from 2.2 V supply voltage. The chip size is 1.87×0.75 mm2

This paper presents an integrated inverted strip- line-like tunable transmission line structure where the propagation velocity can be modified as the characteristic impedance remains constant. As one application of this structure, a mm- wave phase shifter for massive hybrid MIMO applications is implemented in a 45 nm CMOS SOI process. Measurement results at 45 GHz of this phase shifter demonstrate a 79o phase shift tuning range, worst-case insertion loss of 3.3 dB , and effective area of 0.072 mm2. Compared to an on-chip reference phase shifter implemented based on a previously reported tunable transmission line structure, this work achieves 35% less area occupied and 1.0 dB less insertion loss, while maintaining approximately the same phase shift tuning range.

To realize a terahertz (THz) transmitter that supports complex digital modulation with a CMOS process having a sub-THz fmax, an unconventional triple-conversion architecture is introduced. Its first mixer is a quadrature modulator. The second mixer generates a second IF signal with modulated upper and lower sidebands (signal and its image). The third mixer is the frequency quintupler-based, LO-less “quintic mixer” with an amplitude-distortion compensation filter. It up-converts the second IF signal to RF with high linearity using the two modulated sidebands. No LO signal needs to be supplied. A proof-of-concept experiment of the quantic mixer is demonstrated using a CMOS test chip with an on-chip IF receiver. A 16-QAM signal centered around 159 GHz is successfully generated from a modulated second IF signal at 31 GHz.

This paper reports on the investigation of millimeter wave switches, which are based on shunt transistors. The investigation is focusing on the following parts: identifying the optimum transistor gate width, large signal modeling of shunt transistors and the MMIC design. Based on the investigations of the optimum gate width, it will be shown that insertion loss and isolation of a switch are directly correlated to the on-resistance of the transistor. Two SPDT switch MMICs were designed and fabricated, operating in the frequency range from 48 to 150 GHz and from 200 to 300 GHz, respectively. Both switches show low insertion loss, high isolation, high yield and good agreement to the S-parameter simulations, based on the proposed shunt FET model. The proposed W-band and H-band SPDT switch MMICs achieve an insertion loss of 2.7 dB and an output signal dynamic of up to 47 and 15 dB, respectively.

This paper presents a 219 GHz fundamental CMOS oscillator with a 2.08% DC-to-RF efficiency. The proposed structure oscillates at a high fundamental frequency by adopting a capacitive-load reduction technique. In addition, a differential-to-single (DTS) transformer increases the output power by combing the differential signals. The proposed oscillator is fabricated in a 65 nm CMOS process. The measurements show an output power of 0.5 mW at the fundamental oscillation frequency of 219 GHz, while consuming 24 mA from a 1 V supply voltage. This work presents a fundamental oscillator with a higher DC-to-RF efficiency compared to previous state-of-the-art generators between the 200 and 300 GHz frequency range.

A four-way Doherty amplifier architecture with high integration is proposed to address the simultaneous challenges of multi-band capability and high back-off efficiency. Based on this approach, a compact 100 W LDMOS amplifier is designed and characterized in the 1.805 to 2.17 GHz frequency band. It achieves 13.4 dB maximum gain, together with 47 % efficiency at 8 dB back-off, and can be linearized to lower than -59 dBc ACPR level with a 20 MHz wide LTE signal. The fabricated amplifier features a compact size of 50 x 80 mm2.

In this paper, a novel technique is proposed to improve Doherty Power Amplifiers’ (DPAs’) bandwidth and efficiency by manipulating harmonic components to reshape current and voltage waveforms over a continuous bandwidth. Such operation creates a series of continuous high efficiency modes at each frequency over the band, which is referred as Continuous Mode Doherty Power Amplifier (C-DPA) in this paper. Based on the proposed technique, a 30-Watts broadband C-DPA is designed over the entire mainstream communication frequency band 1.65-2.75GHz. Using a 20MHz, 7.5dB PAPR LTE signal, the fabricated DPA is measured and linearized. According to the measured results, the designed DPA exhibits 46%-62% modulated efficiency over the designed 1.1GHz frequency range while maintaining Adjacent Channel Power Ratio (ACPR) below -45dBc. To the best of the authors’ knowledge, this is the state-of-the-art performance of DPAs.

A new outphasing signal splitter for a radio frequency (RF) single input Chireix power amplifier without using digital signal processing is introduced. Input signal phase splitting versus power for outphasing operation with load modulation is obtained by using only a linear circuit exploiting input impedance variation of non-ideal devices. A 52.6 dBm peak output power, 6 dB back-off Chireix power amplifier is built operating at 2.17 GHz. More than 50% drain efficiency is maintained over 5.7 dB output power back-off range.

In this paper, a novel multi-stage DPD with constrained feedback bandwidth is proposed. The proposed DPD effectively compensates for the nonlinear distortion in closely spaced multi-carrier power amplifiers (PAs). By extracting the PA static nonlinearity characteristics from the bandwidth-constrained signals, and separately processing the multi-carriers input, the proposed DPD reduces the feedback bandwidth and hence the sampling rate. Moreover, it effectively suppresses the spectral regrowth within the off-carrier regions along the transmission bandwidth, not only the adjacent channels. Experimental results have validated improved performance on a 60 MHz LTE-advanced signal, even when the analog to digital converter sampling rate is constrained to 61.44 Msps. Thus, it can significantly decrease the difficulties in system design and reduce implementation cost.

A linearization algorithm for the envelope supply voltage waveform is proposed for an open-loop multi-switcher envelope tracking power amplifier (ETPA). To maintain the fidelity of the supply voltage, we develop a two-step method comprising “non-linear pre-emphasis” and “envelope memory polynomial digital predistortion”, where the captured supply voltage of an RFPA is used. An ETPA is demonstrated using a 45 V CMOS multi-switcher envelope modulator and a 2.14 GHz 30 W GaN RFPA. The measured envelope absolute RMS error and ACLR are improved to 1.3% and -45 dBc from 6.4% and -36dBc, respectively, compared with a conventional pre-emphasis.

Recent advances in high power millimeter wave (mmW) Gallium Nitride (GaN) technology has enabled the development of a high power solid state W-band transmitter with an unprecedented 7kW Continuous Wave (CW) output power. The transmitter coherently sums a total of 8,192 1W+ GaN Power Amplifier (PA) Monolithic Microwave Integrated Circuits (MMICs) using spatial combining. This accomplishment represents a two-orders-of-magnitude improvement in W-band solid state power generation over previously published results.

Two power amplifier MMICs, designed for minimal footprint, and a low insertion loss microstrip to waveguide transition are presented at 220GHz. The two-stage power amplifier ((260x1120)μm²) exhibits 13.5mW of output power and 13.3dB of gain at 207GHz. The four-stage power amplifier, designed in a (260x2085)μm² area, provides an output power higher than 15mW associated with 19.8dB of gain up to 220.5GHz, with a peak output power of 28mW measured at 211.5GHz. The microstrip to waveguide transition was designed to fit within a width of 280μm, in order to limit the excitation of unwanted substrate modes. These three devices were designed for integration on a single, rectangle chip transmitter.

Two solid-state power amplifiers with record PAE and 100-130mW power in 250nm InP HBT are reported. The 71-95GHz PA demonstrates 20.7dB S21 and 25GHz 3dB bandwidth. Pout is 105-138mW (21-36% PAE). At 81GHz, 135.6mW Pout is achieved with 36.0% PAE. At 81GHz with reduced bias, 129.6mW Pout is achieved with 40.0% PAE. The 96-120 GHz PA demonstrates 17.8dB S21 and 26GHz 3dB bandwidth. Pout is 84.9-107mW. At 102.5GHz, 98.1mW Pout is achieved with 21.2% PAE. The amplifiers utilizes a novel, stackable power cell topology for multi-finger HBTs, where 8-way cell combining can be realized for future 0.6-0.8W designs. This work represents record PAE for 100mW PA’s at these frequencies. 40% PAE at E-band (81GHz) is demonstrated for the first time under class-A bias, as well as PAE >23% across the 71-76,81-86 and 92-95GHz bands. The 18.9-22.5% PAE at 100mW power for the 96-120GHz PA is 1.5-3× improvement to state-of-the-art PAE.

This paper reports on an efficient transmitter monolithic microwave integrated circuit (TX MMIC) suitable for high-speed wireless communication. In order to achieve high output power, the TX is based on a direct modulation approach, containing a stacked-FET voltage-controlled oscillator (VCO) and an amplitude modulator. Thus, the modulation scheme is based on amplitude-shift keying (ASK). The MMIC utilizes a 50 nm metamorphic high-electron-mobility transistor (mHEMT) technology. The stacked-FET oscillator generates the carrier signal and achieves an output power of about 14 dBm. The carrier frequency can be tuned from 87.8 to 98.2 GHz. Due to the FET-stacking approach the amplitude modulator can be simplified to a single-pole, single-throw (SPST) switch. Hence, the transmitter MMIC achieves a peak output power of 12.5 dBm and a maximum data rate of 18 Gbit/s. The maximum continuous wave (CW) efficiency of the entire TX MMIC yields 17.6 %.

A solid-state 216-GHz communication link is presented. It utilizes a novel mixer-less transmitter technique to achieve efficient complex modulation using frequency multipliers (which are inherently nonlinear). The transmitter operates with coherent power combining of two frequency multiplier chains to achieve precise linear amplitude and phase modulation despite the strong nonlinearity of the multipliers and the saturated power amplifiers. A 16-QAM modulation signal is demonstrated with a transmitted output power of 100 mW.

This paper presents a wideband 330 GHz frequency quadrupler using 0.8 μm transferred substrate (TS) InP-HBT technology. The process includes a heat-spreading diamond layer, which improves the power handling capability of the circuit. The quadrupler delivers -7 dBm output power at 325 GHz, at a DC consumption of only 40 mW, which corresponds to 0.5 % of efficiency. It achieves 90 GHz bandwidth and exhibits very low unwanted harmonics. This demonstrates the potential of the transferred-substrate process for THz frequencies.

This paper presents H-band down-conversion and up-conversion mixers implemented in a 250-nm InP double heterojunction bipolar transistor technology. The mixers are aimed to achieve a wide IF bandwidth and high conversion gain for high-speed wireless communication. The- mixer core employs a Gilbert cell pumped by a fundamental LO signal, leading to high conversion gain and high isolation. To achieve a wide IF bandwidth, the inductive-peaking, Cherry-Hooper, and staggered-tuned techniques are used at IF output of the down-conversion mixer. The down- and up-conversion mixers exhibit measured conversion gain of 7.5 and -5.2 dB with 3-dB SSB IF bandwidth of 20 and 25 GHz at LO frequency of 270 and 280 GHz, respectively.

This paper reports the first broadband, high-power solid-state power amplifier operating at W-band (75-110 GHz) frequencies. Using a broadband 2W MMIC chip, we report a radial combiner that effectively combines 24 of these MMICs to achieve an average CW output power of 37 W across the 75 to 100 GHz band, and an output power of 50 W below 80 GHz. The computed combining efficiency is, on average, 84.5% across the band. Using forced air cooling (in a wind-tunnel), the amplifier produces an output power of 45.6 dBm (35 W) ±1.4 dB across the 75 to 100 GHz band.

This paper presents the design of a high power, broadband sequential power amplifier with Doherty-type active load modulation (SPA-D) for DVB-T applications. By designing the SPA-D at device level, the bandwidth limitation due to device parasitics and the frequency dependence of peaking output impedance can be mitigated. External capacitors are used in combination with the device output capacitances and package parasitics to form very short transmission lines (TL) with characteristic impedances equal to the corresponding device optimum impedances. In this way, the fractional bandwidth (FB) of SPA-D can be extended up to 60%. The high power SPA-D demonstrator exhibits measured drain efficiency of 45%-67.5% at 8-10 dB power back-off (BO) and 54%--79% at peak power of > 100 W over 460 MHz-830 MHz (~ 57% FB). To the best of our knowledge, this PA has the highest performance in terms of efficiency and bandwidth to date.

The design, realization, and characterization of a K-band high power amplifier with a saturated output power of 40 dBm is described in this paper. The amplifier is realized using a 250 nm gate length AlGaN/GaN HEMT MMIC technology on semi-insulating SiC substrates. The two-stage amplifier is designed with two 6x90 µm HEMT cells in the driver and four 8x100 µm HEMT cells in the final stage and thus exhibits a relatively aggressive staging ratio of 1:3. When measured with a supply voltage of 32 V, the amplifier delivers a saturated output power of 40 dBm at 18 GHz. The peak PAE at this frequency is 30 %, and the linear gain exceeds 20 dB. These results are state-of-the-art performance with regard to power/efficiency at K-band.

This paper reports a fully integrated impulse radiator with the capability of radiating impulses with 4ps FWHM and reconfigurable amplitude. The radiated impulse has an SNR>1 bandwidth of 197GHz. The peak radiated power at 54GHz is 8.7dBm with a 13.6dBm peak EIRP. A nonlinear Q-switching impedance (NQSI) is introduced to tune the impulse amplitude. Furthermore, a 2-bit impulse amplitude modulation is achieved through an on-chip four-way impulse combining based on an inductive impulse coupling scheme. In addition to performing the conventional frequency-domain measurement, for the first time, an ultra-wideband THz time-domain spectroscopy (THz-TDS) system is utilized to characterize ICs in time-domain, capturing the real time-domain waveform of a 4ps impulse. The fully-integrated impulse radiator is implemented in a 0.13µm SiGe BiCMOS process with a die area of 1mm2 and it consumes 170mW.

This paper presents a wireless synchronization receiver using sub-8psec pulses. A novel self-mixing technique is introduced to detect low-power picosecond impulses and extract the repetition rate with a low timing jitter. The chip is fabricated in a 0.13µm SiGe BiCMOS process and a record time transfer accuracy of 376fsec is achieved. The receiver, which is integrated with a broadband on-chip antenna, successfully detects a picosecond pulse train with a 3.1GHz repetition rate and generates an output locked to this rate with a phase noise of -89 dBc/Hz at 100 Hz frequency offset. The chip consumes 146 mW from a 2.5V supply and occupies an area of 1.89mm2.

A dual band F-band packaged transceiver at 95GHz and 130GHz in 65nm CMOS technology is presented. The transceiver architecture is based on a bi-directional operation with a maximum data rate of up to 12Gbps per band. Maximum output power on-chip of -0.5dBm and -1.5dBm were achieved in the low band (95GHz) and high band (130GHz) respectively and 12+12Gbps modulated signals are measured off-chip in the transmit mode. In the receive mode a BER

A QAM-capable 300-GHz transmitter operating above fmax, covering a 30-GHz bandwidth with multiple channels, was recently reported. A key enabling component was a tripler-based up-conversion mixer called the “cubic mixer.” This paper theoretically and experimentally studies the S/N characteristics of such a mixer and elucidates the condition for realizing high single-channel data-rate. 30 Gb/s and 21 Gb/s with, respectively, 32QAM and 64QAM are achieved under optimal conditions. These are faster than the previously reported per-channel data-rate of 17.5 Gb/s.

This paper presents a high efficiency 165 GHz OOK transmitter on a 65nm CMOS technology, including a transformer based impedance boosting fundamental cross-coupled oscillator followed by a high-speed and high on-off ratio SPST switch based modulator. The transmitter demonstrates the highest DC-to-RF efficiency (10.6%) beyond 140 GHz in silicon processes, with a high output power (0.66 dBm), a high on-off ratio (> 32 dB) and a low phase noise (-105.4 dBc/Hz @ 1 MHz offset). The standalone oscillator also demonstrates the record DC-to-RF efficiency of 25.9% beyond 140 GHz in silicon processes. The transmitter is designed compact with the core area of 240 µm × 130 µm.

In this work, a monolithically integrated segmented driver and Mach-Zehnder modulator (MZM) in 0.25 μm SiGe:C BiCMOS technology is presented. The driver and the modulator are divided in 16 segments and the MZM has a total length of 6.08 mm. The driver has a maximum gain of 14.5 dB. Electro-optical time-domain measurements were performed and an optical eye-diagram with more than 13 dB of extinction ratio at 28 Gb/s is demonstrated. The driver dissipates a total of 2 W of DC power. To the best knowledge of the authors, the presented work shows the highest extinction ratio achieved at 28 Gb/s in silicon modulators.

This paper outlines the design and electrical characterization of an optical modulator driver fabricated in a 0.13 µm BiCMOS SiGe:C technology. The prototype, optimized for hybrid assembly with a 15-segment InP segmented Mach Zehnder modulator (SE-MZM), displays integrated 4-bit digital to-analog converter (DAC) functionality, allowing the generation of PAM-16 modulation format. The driver delivers a differential output swing of 2.5 Vpp across all 15 segments, dissipating less than 1 W of power. Electrical eye diagrams up to 40 Gb/s are reported, demonstrating the capability for high speed 4 x 40 Gb/s electro-optical transmission. The devised hybrid solution proves the potential of SiGe HBT drivers for achieving higher speeds over their CMOS counterparts, with comparable power dissipation.

In this work, we report a highly linear quantum well Mach-Zehnder (MZ) intensity modulator. The MZ modulator’s linearity was enhanced by canceling the nonlinearities from the MZ interferometer and the nonlinear phase modulation. The MZ modulator demonstrated over 24 dB improvement in nonlinearity distortion levels compared with that of a LiNbO3 MZ modulator. It achieved a third-order intercept point in phase perturbation of 2.6 pi RMS. This is sufficient to allow an RF/photonic link to achieve over 120 dB∙Hz2/3 spurious-free dynamic range (SFDR) with low photocurrent (

A low-cost linearization technique is proposed to improve RF signal power and suppress third order intermodulation distortion (IMD3) in radio-over-fiber (RoF) transmission systems. A directly modulated laser (DML) and an electro-absorption modulator integrated laser (EML) in C-band are used for optical subcarrier modulation. The IMD3s induced by the two optical subcarrier modulations are suppressed by each other through adjusting the bias voltage of the electro-absorption modulator in the EML. In our initial experiments, the spurious free dynamic range (SFDR) is improved by more than 3.5 dB and output power at 1 dB compression point is improved by 4.3 dB.

Based on a photonic microwave phase shifter, a microwave image-reject mixer (IRM) with all the mixing spurs suppressed is proposed by using a dual-polarization dual-drive Mach-Zehnder modulator (DPol-DMZM). A proof-of-concept experiment is conducted. Due to the wide band and precise 90-degree phase shift introduced by the photonic microwave phase shifter, the image rejection ratio reaches ~60 dB when the RF and LO frequencies are within 10-40 GHz. In addition, the mixing spurs are all suppressed below the noise floor.

A photonics-based direct conversion RF receiver has been realized and characterized. The innovative architecture uses coherent optical techniques to perform a fast and wideband scan of the RF spectrum avoiding bulky multiple crystal oscillators. The direct conversion approach based on photonics enables filtering the input signal spectrum by means of a simple electrical low pass filter, and provide total immunity to local oscillator self mixing and to RF to baseband feedthrough, which are typical drawbacks of conventional direct conversion receivers. The experimental validation shows an operating bandwidth of 0.5÷10.5 GHz and instantaneous bandwidth of 1 GHz, with linear dynamic range of 141 dB/Hz and spurious-free dynamic range of 107 dB/Hz2/3. Further system developments will enhance the operating bandwidth up to 40 GHz. Implementing the scheme through integrated photonics technologies will also ensure high environmental stability and reduced size weight and power consumption.

A room temperature LNA suitable for Square Kilometer Array band 1 (0.35–1.05 GHz) has been designed, fabricated and tested. The design is based on InP HEMTs, and focused on minimizing losses in the input matching network. Noise measurement methods in two different labs were used to confirm the 10 K noise temperature of the LNA. The gain was flat at 50 dB and the input and output return loss better than 10 dB in most of the band.

Next generation radio telescopes will have a very large number of antenna elements. For such systems, ultra-low-noise ambient-temperature integrated CMOS receivers can address some design challenges, such as size, weight, power consumption, and cost. This paper describes the development of one such receiver. Developed in 65-nm TSMC CMOS, it operates between 0.7 and 1.5 GHz and achieves minimum noise temperatures of 16 K at 1.5GHz and power gain of 70 dB, while consuming 265 mW of power.

The design and characterization of a cryogenic silicon germanium integrated circuit amplifier operating at a center frequency of 22 GHz is presented. The packaged amplifier is measured at 15 K and achieves a gain of 25 dB and a noise temperature below 35 K, which is consistent with simulated performance. It is believed that this is the first reporting of a cryogenic silicon germanium low-noise amplifier operating above 10 GHz and represents the lowest reported noise temperature for any silicon based low-noise amplifier operating at these frequencies.

Coherent circuits based on superconducting elements hold tremendous promise for the practical implementation of quantum information technology: advanced computation, cryptography, and hardware simulation of complex materials systems are envisioned applications. Such circuits are essentially engineered atoms with level transitions in the 4-8 GHz regime; as such "read" and "write" operations are performed with the aid of fast microwave pulses and low-noise amplifiers, respectively. Recent advances in cavity-based superconducting parametric amplifiers have enabled real-time measurement and feedback in one and two qubits. We demonstrate a novel Josephson junction transmission-line based traveling-wave amplifier which employs sub-wavelength phase matching resonators to achieve high gain, several GHz of bandwidth, and near quantum-noise limited performance. Such devices will enable multiplexed qubit readout in integrated architectures comprised of a variety of microwave frequency analog and digital superconducting technologies: signal sources, multiplexers, ADCs, DACs, mixers, and amplifiers.